1. Field
This invention relates to integrated circuits, and particularly to fabricating high-k dielectric gate structures having improved resistance to the growth of silicon dioxide at the dielectric/silicon-based substrate interface.
2. Description of Background
Integrated circuits often employ active devices known as transistors such as field effect transistors (FETs). A metal-oxide-semiconductor field effect transistor (MOSFET) includes a silicon-based substrate comprising a pair of impurity regions, i.e., source and drain junctions, spaced apart by a channel region. A gate electrode is dielectrically spaced above the channel region of the silicon-based substrate. The junctions can comprise dopants which are opposite in type to the dopants residing within the channel region. MOSFETs comprising n-type doped junctions are referred to as NFETs, and MOSFETs comprising p-type doped junctions are referred to as PFETs. The gate electrode can serve as a mask for the channel region during the implantation of dopants into the adjacent source and drain junctions. An interlevel dielectric can be disposed across the transistors of an integrated circuit to isolate the gate areas and the junctions. Ohmic contacts can be formed through the interlevel dielectric down to the gate areas and/or junctions to couple them to overlying interconnect lines.
The gate dielectric interposed between the channel and the gate electrode of MOSFETs was once primarily made of thermally grown silicon dioxide (oxide). Due to the need for integrated circuits having higher operating frequencies, the thickness of the oxide gate dielectric has steadily decreased to increase the gate capacitance and hence the drive current of MOSFETs. However, as the thickness of the oxide gate dielectric has decreased, leakage currents through the gate dielectric have increased, leading to reduced device reliability. As such, the oxide gate dielectric is currently being replaced with dielectrics having higher dielectric constants (k) than oxide, i.e., k>3.8. Such “high-k dielectrics” provide for increased gate capacitance without the detrimental effect of leakage current.
MOSFETs that include a metal gate electrode/high-k dielectric stack suffer from the drawback of experiencing oxide growth at the interface of the high-k dielectric and the silicon-based substrate. This oxide growth can occur as a result of ambient oxygen and/or oxygen in areas of the integrated circuit near the MOSFET diffusing to the high-k dielectric/substrate interface. This oxygen diffusion is more likely to occur when the integrated circuit is subjected to high temperatures during anneal steps and/or thermal steps. The oxide growth can undesirably increase the thickness of the gate dielectric with an oxide having a lower k value than that of the original gate dielectric. The magnitude of the oxide growth is dependent upon the size of the MOSFET and the nature of nearby structures. Unfortunately, the oxide growth can undesirably cause a “width effect” in narrow width (or length) MOSFETs that is often manifested by non-area scaling of the gate leakage current in such small area devices. Device characteristics of the width effect include a shift in MOSFET threshold voltage (VT) and drive current degradation.